The present invention relates to a signal processing device and, more particularly, to an audio data transmission circuit which performs a data transmission in a serial form.
Conventionally, a serial data transmission circuit of this kind is so arranged that each of the input portion and output portion thereof is provided with a separate data shift circuit.
Disadvantages in such conventional serial data transmission circuit are that the provision of the two data shift circuits results in an increase in the size of the circuit and that, in order to make the serial data transmission circuit adaptable to various kinds of serial data, whose data lengths are different from one another or operable under various kinds of transmission clock signals, it is necessary to provide at an input and output portion, respectively, the data shift circuits of their own, which results in a still further increase in the overall circuit scale.
In the conventional serial data transmission circuit referred to above, even in the instances where the serial data inputted is to be outputted in the state as inputted so as not to leave any interruption in the transmission data, for example, when the operation mode in the signal processing device is changed, that is, where the data as inputted may be outputted without any changes at the digital signal processing device, it is necessary to effect the data transfer from the one data shift circuit at the input side to the other data shift circuit at the output side. For this process, the internal data bus is occupied, which prevents the signal processing block from performing any other processes independent of the above data transfer and which results in the lowering of the overall processing speed.
Furthermore, there is a disadvantage that the conventional arrangement, wherein the input data shift circuit and the output data shift circuit are independent from each other, unavoidably causes the occurrence of jitter between the transmission clock signal for the input side circuit and that for the output side circuit.